1. Field of the Invention
The invention relates to a method of detecting an integrated circuit in failure among a plurality of integrated circuits, and more particularly to a method of doing so, based on spectrum which is a result of analyzing a frequency of a current running through an integrated circuit when a test signal is applied to the integrated circuit.
The invention relates also to an apparatus for detecting an integrated circuit in failure among a plurality of integrated circuits, and more particularly to an apparatus for doing so, based on spectrum which is a result of analyzing a frequency of a current running through an integrated circuit when a test signal is applied to the integrated circuit.
The invention relates further to a recording medium readable by a computer, storing a program therein for causing a computer to either carry out the above-mentioned method or act as the above-mentioned apparatus.
2. Description of the Related Art
A method of detecting an integrated circuit in failure among integrated circuits has usually been carried out in order to detect and remove integrated circuits which are not capable of performing desired operations due to defectiveness in fabrication steps, and ship only integrated circuits which can properly operate.
For instance, the inventor had suggested a method of detecting an integrated circuit in failure in Proceedings of the 1998 IEICE General Conference C-12-8 “Diagnosis of failure in an integrated circuit by analysis of a current with power spectrum”. In this method, a current running through an integrated circuit while the integrated circuit is in operation is analyzed with respect to a frequency, to thereby detect an abnormal current caused by defectiveness in fabrication steps.
Japanese Unexamined Patent Publication No. 9-33604 has suggested a method of identifying a failure mode, comprising the steps of detecting a logic operation test pattern in which a power source current abnormally runs through CMOS logic circuit, which is one of internal circuits of an integrated circuit, in an amount greater than a predetermined amount while the CMOS logic circuit stops its logic operation, when a logic operation test pattern is input into the CMOS logic circuit through an input terminal thereof, extracting a characteristic between a power source voltage and a power source current with the detected logic operation test pattern being input into the CMOS logic circuit, and comparing the thus extracted characteristic between a power source voltage and a power source current to similarity between a failure mode and data between a power source voltage and a power source current, stored in a database, to thereby identify a failure mode occurring in the CMOS logic circuit.
Japanese Unexamined Patent Publication No. 9-211088 has suggested a method of detecting a failure in CMOS integrated circuit by observing a static power source current independent of switching of a transistor, among a current running through CMOS integrated circuit when a test pattern is applied to CMOS integrated circuit. The suggested method is carried out in an apparatus including means for repeatedly applying a test pattern to CMOS integrated circuit under test, means for measuring a power source current supplied to CMOS integrated circuit under test, and means for measuring power spectrum of the detected power source current. The method includes the step of judging whether CMOS integrated circuit is in failure or not by observing a magnitude of power having a predetermined frequency band, among the power spectrum of the power source current.
Japanese Unexamined Patent Publication No. 10-301843 has suggested a data processor comprising a main memory including a plurality of memories, and a plurality of processors transmitting a plurality of requests of data transfer to the main memory for each unit of data, and processing data transmitted from the main memory. The plurality of memories include means for detecting bank competition which occurs by the requests transmitted from the processors, and transmit a bank competition signal to the processors, and a circuit measuring a period of time during which bank competition occurs, based on the bank competition signal.
Japanese Unexamined Patent Publication No. 11-2663 has suggested a method of detecting a failure in CMOS integrated circuit by observing a static power source current running CMOS integrated circuit when a series of test patterns is repeatedly applied to CMOS integrated circuit from LSI tester. The method includes the steps of repeatedly applying test patterns to an integrated circuit under test and a reference integrated circuit which is identical with the integrated circuit under test and is not in failure, measuring a difference between a current running through the integrated circuit under test and a current running through the reference integrated circuit, and judging whether the integrated circuit under test is in failure or not, based on a magnitude of spectrum component having a repetition frequency at which the test patterns are repeated.
Japanese Unexamined Patent Publication No. 11-94917 has suggested a method of testing a semiconductor device on which CMOS circuit is mounted, comprising the steps of inputting a clock signal into the semiconductor device, and calculating a maximum operating frequency on the basis of an inverse number of a delay time during which a power source current starts increasing at a clock operation timing and then becomes steadily equal to zero.
However, the above-mentioned methods are all accompanied with a problem that a reference, that is, data about a power source current of an integrated circuit having no failure has to be prepared in advance in order to test integrated circuits under test.
It is quite difficult to prepare such a reference. The reason is as follows. Data about a power source current is analog data, and is much influenced by processing conditions in fabrication of an integrated circuit. As a result, there is slight fluctuation among data about a power source current of integrated circuits having no failures. Hence, it is quite difficult to define a reference to be used for testing integrated circuits as to whether they are in failure or not.